ASIC Package SI/PI Engineer

OpenAI's Hardware organization develops AI-native silicon and system-level solutions for advanced AI workloads, co-designing chips, systems, tools, and methodologies for OpenAI's supercomputing platform.

Seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for advanced AI/HPC silicon and package design, focusing on high-speed SerDes and memory channels, 2.5D/3D package SI/PI, power-delivery-network optimization, and simulation-to-measurement correlation.

• Own SI/PI architecture and analysis for advanced AI ASIC packages from feasibility through production.
• Develop and optimize high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and chiplet/die-to-die interfaces.
• Perform package, interposer, and substrate modeling using 2D/3D electromagnetic solvers.
• Define and optimize package stack-ups, transmission-line structures, via transitions, breakout structures, return paths, ground shielding, bump maps, and ball maps.
• Develop channel loss, crosstalk, impedance, skew, return-loss, and link-budget requirements.
• Perform package-level PDN analysis including impedance, loop inductance, DCIR, EM, dynamic voltage droop, current distribution, and decoupling optimization.
• Drive die/package co-design including bump/BGA assignment, stack-up optimization, power/ground allocation, and high-speed I/O placement.
• Develop simulation methodologies and automation flows for design-space optimization and SI/PI sign-off.

Required: 5+ years in signal integrity, power integrity, high-speed interconnect design, PDN design, and package electrical design; strong understanding of SI/PI fundamentals; hands-on experience with EM and SI/PI simulation tools such as Synopsys HSPICE, Ansys EDT, HFSS-PI, SIwave, Cadence Clarity, Sigrity PowerSI/PowerDC; experience with package layout environments like Cadence APD/SIP; experience developing automated design optimization flows; strong communication skills.

Preferred: advanced 2.5D/3D packaging, HBM integration, memory architecture, high-speed lab validation, knowledge of package/PCB materials.

$266K – $445K plus equity.

Apply via the provided link.