ASIC Package SI/PI Engineer

OpenAI's Hardware organization develops AI-native silicon and system-level solutions for advanced AI workloads. The team co-designs chips, systems, tools, and methodologies to deliver faster, more efficient, and production-ready hardware for OpenAI's supercomputing platform.

We are seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for advanced AI/HPC silicon and package design. This role focuses on high-speed SerDes and memory channel architecture, advanced 2.5D/3D package SI/PI, substrate to package co-design, power-delivery-network optimization, electromagnetic modeling, and simulation-to-measurement correlation.

• Own SI/PI architecture and analysis for advanced AI ASIC packages from early feasibility studies through production.
• Develop and optimize high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and chiplet/die-to-die interfaces.
• Perform package, interposer and substrate modeling using 2D/3D electromagnetic solvers.
• Define and optimize package stack-ups, transmission-line structures, via transitions, breakout structures, return paths, ground shielding, bump maps, and ball maps based on SI/PI requirements.
• Develop channel loss, crosstalk, impedance, skew, return-loss, and link-budget requirements, and translate them into actionable package layout guidelines.
• Perform package-level PDN analysis, including impedance, loop inductance, DCIR, EM, dynamic voltage droop, current distribution, decoupling optimization, and power/ground architecture.
• Drive die/package co-design, including bump/BGA assignment, stack-up optimization, power/ground allocation, high-speed I/O placement, and package routing architecture.
• Develop simulation methodologies and automation flows for early architecture exploration, design-space optimization, and repeatable SI/PI sign-off.

• 5+ years of experience in signal integrity, power integrity, high-speed interconnect design, PDN design and package electrical design.
• Strong understanding of signal-integrity and power-integrity fundamentals, including transmission-line behavior, impedance, loss, crosstalk, return paths, power-distribution networks, inductance, decoupling, voltage droop, and current distribution.
• Hands-on experience with electromagnetic and SI/PI simulation tools such as Synopsys HSPICE, Ansys EDT, HFSS-PI, SIwave, Cadence Clarity, Sigrity PowerSI/PowerDC, or equivalent.
• Experience with package layout environments such as Cadence APD/SIP, including the ability to review and modify package structures for SI/PI optimization.
• Experience developing automated design optimization flows for model extraction, simulation setup, post-processing, design-space exploration, or layout optimization.
• Strong communication skills and the ability to work effectively across ASIC, package, PCB, system, mechanical, thermal, power, validation, and manufacturing teams.

• Hands-on experience with advanced 2.5D/3D packaging, silicon or organic interposers, bridge technologies, HBM integration, IVR integration, or large-body AI/HPC packages.
• Experience developing early-stage SI/PI feasibility methodologies that support chip and package architecture decisions.
• Experience with memory architecture and high-speed memory interfaces, including HBM and DDR/LPDDR.
• Experience with high-speed laboratory validation using VNA, spectrum analyzers, TDR/TDT, high-bandwidth oscilloscopes, and probe-based measurements.
• Knowledge of package and PCB material properties, including dielectric constant, loss tangent, copper roughness, and manufacturing variation.

Salary range: $266K – $445K. Offers Equity.

Apply via the OpenAI careers page.